View MAX13342E_4656023.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX13342E/max13345e usb-compliant trans- ceivers are designed to minimize the area and external components required to interface low-voltage asics to usb. the devices comply with usb 2.0 specification for full-speed-only (12mbps) operation. the transceivers include an internal 3.3v regulator, an internal 1.5k ? d+ pullup resistor, and built-in ?5kv esd protection cir- cuitry to protect the usb i/0 ports (d+,d-). the max13345e also has internal series resistors, allowing it to be wired directly to a usb connector. these devices operate with logic-supply voltages as low as +2.3v, ensuring compatibility with low-voltage asics. a low-power mode reduces current consump- tion to less than 45?. an enumerate function controls the d+ pullup resistor, allowing devices to logically dis- connect while remaining plugged in. the MAX13342E has controlled output impedance of 2 ? (max) on d+/d-, allowing the use of external switch- es to multiplex two different usb devices onto a single usb connector. the max13345e has 43.5 ? (max) internal resistors on d+/d- for direct connection to the usb connector. the MAX13342E/max13345e are equipped with dat and se0 interface signals. these transceivers provide a usb detection function that monitors the presence of usb v bus and signals the event. these devices operate over the extended -40c to +85? temperature range and are available in ucsp 2.0mm x 1.5mm and 14-pin tdfn (3mm x 3mm) packages. ucsp is a trademark of maxim integrated products, inc. applications pdas pc peripherals cellular telephones data cradles mp3 players features usb 2.0 (full-speed, 12mbps)-compliant transceiver internal pullup v bus detection internal series resistors (max13345e) 15kv (hbm) esd protection on d+, d-, and v bus enumeration input controls d+ pullup resistor supports 3-wire dat/se0 interface +2.3v to +3.6v interface voltage (v l ) no power-supply sequencing required low usb output impedance (MAX13342E) MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors ________________________________________________________________ maxim integrated products 1 19-0621; rev 0; 10/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information MAX13342E system voltage supply v l system interface bd dat seo 1 f 1 f 0.1 f gnd d- d+ v trm v bus sus enum oe usb connector 31.6 ? 31.6 ? typical operating circuits pa rt pin- pa ck a g e t o p m a rk pk g c o de MAX13342Eetd + 14 td fn- e p ( 3mm x 3m m ) ac z t1433- 2 m ax13342e e bc + * 12 u c s p ( 2.0m m x 1.5m m ) ac u b12- 3 m a x1 3 3 45 eetd + 14 td fn- e p ( 3mm x 3m m ) ad a t1433- 2 m ax13345e e bc + * 12 u c s p ( 2.0m m x 1.5m m ) ac x b12- 3 * future product?ontact factory for availability. + denotes lead-free package. ep = exposed pad. pin configurations and selector guide appear at end of data sheet. typical operating circuits continued at end of data sheet.
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages refer to gnd unless otherwise noted.) supply voltage (v bus ) .............................................-0.3v to +6v system supply voltage (v l ) .....................................-0.3v to +6v output of internal regulator (v trm ) .........-0.3v to (v bus + 0.3v) input voltage (d+, d-) ..............................................-0.3v to +6v sus, bd ........................................................-0.3v to (v l + 0.3v) enum, se0, dat ..........................................-0.3v to (v l + 0.3v) short-circuit current to v bus or gnd (d+, d-) ..............150ma maximum continuous current (all other pins) ..................15ma continuous power dissipation (t a = +70 c) 14-pin tdfn (derate 18.5mw/ c above +70 c) .......1482mw 4mm x 3mm ucsp (derate 6.5mw/ c above +70 c) ..............................518mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c bump soldering ...............................................................+235 c lead soldering (10s) ...................................................... +300 c electrical characteristics (v bus = +4.0v to +5.5v, v l = +2.3v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v bus = +5.0v, v l = +2.5v, t a = +25 c.) (note 1) parameter symbol conditions min typ max units supply inputs (v bus , v trm , v l ) v bus input range v bus 4.0 5.5 v v l input range v l 2.3 3.6 v reg ul ated s up p l y- v ol tag e outp ut v trm 3.0 3.3 3.6 v operating v bus supply current i vbus full-speed transmitting/receiving at 12mbps, c l = 50pf on d+ and d- 10 ma operating v l supply current i vl ful l - sp eed tr ansm i tti ng /r ecei vi ng at 12m b p s, c l = 15pf receiver outputs, v l = 2.5v 1.5 ma full-speed idle, v d+ >2.7v, v d- <0.3v 500 full-speed idle and se0 supply current i vbus ( idle ) se0: v d- <0.3v, v d+ <0.3 500 a static v l supply current i vl ( static ) full-speed idle, se0 or suspend mode 10 a suspend supply current i vbus ( susp ) se0 = dat= open; sus = oe = high 30 45 a disable-mode supply current i vbus ( dis ) v l = gnd or open 25 a sharing-mode v l supply current i v l ( s h arin g ) v bus = gnd or open, oe = low, se0 = dat = low or high, sus = high 5a d+/d- supply current i d+/d- v bus = gnd or open 20 a v bus power-supply detection threshold v th_vbus v l > 2.3v 0.8 3.6 v v bus power-supply detection hysteresis v vbushys 100 mv v l power-supply threshold v th_vl 850 mv
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors _______________________________________________________________________________________ 3 electrical characteristics (continued) (v bus = +4.0v to +5.5v, v l = +2.3v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v bus = +5.0v, v l = +2.5v, t a = +25 c.) (note 1) parameter symbol conditions min typ max units digital inputs and outputs (dat, se0, oe , enum, sus, bd) input-high voltage v ih 0.7 x v l v input-low voltage v il 0.3 x v l v output-voltage high v oh i source = 2ma v l - 0.4 v output-voltage low v ol i sink = 2ma 0.4 v input leakage current i lkg -1 +1 a input capacitance measured from input to gnd 10 pf analog inputs and outputs (d+/d-) differential input sensitivity v id |v d+ - v d- | 200 mv differential common-mode voltage range v cm includes v id range 0.8 2.5 v single-ended input voltage high v ihse 2.0 v single-ended input voltage low v ilse 0.8 v receiver single-ended hysteresis v hys 200 mv output-voltage low v old r l = 1.5k ? from d+ or d- to 3.6v 0.3 v output-voltage high v ohd r l = 15k ? from d+ or d- to gnd 2.8 3.6 v off-state leakage current tri-state driver -1 +1 a transceiver capacitance c ind measured from d+ or d- to gnd 20 pf MAX13342E 4 14 driver output impedance r out max13345e 28 43 ? internal pullup resistor r pu 1.425 1.500 1.575 k ? input impedance z in drivers off, tri-state driver, enum = 0, v d+ , v d- = 0 or +3.6v 1m ? linear regulator external capacitor c out compensation of linear regulator 1 f esd protection (d+, d-) human body model 15 kv iec 61000-4-2 air-gap discharge 8kv iec 61000-4-2 contact discharge 8kv
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 4 _______________________________________________________________________________________ timing characteristics (v bus = +4v to +5.5v, v l = +2.3v to +3.6v, enum = v l , t a = t min to t max , unless otherwise noted. typical values are at v bus = +5v, v l = +2.5v, t a = +25 c.) (note 1) parameter symbol conditions min typ max units transmitter ( c l = 50pf) rise time t fr 10% to 90% of |v ohd -v old | with an external 31.6 ? series resistor (MAX13342E), figures 3, 8 420ns fall time t ff 10% to 90% of |v ohd -v old | with an external 31.6 ? series resistor (MAX13342E), figures 3, 8 420ns rise-and-fall time matching (note 1) t lr /t lf figures 3, 8 90 110 % output signal crossover (note 2) v crs_l , v crs_f figure 4 1.3 2 v t plh_drv low-to-high transition, figures 4, 8 v l > 2.3v 20 driver propagation delay t phl_drv high-to-low transition, figures 4, 8 v l > 2.3v 20 ns t pzh_drv off-to-high transition, figures 5, 8 v l > 2.3v 18 driver-enabled delay time t pzl_drv off-to-low transition, figures 5, 8 v l > 2.3v 18 ns t phz_drv high-to-off transition, figure 5, 9 v l > 2.3v 18 driver disable delay t plz_drv low-to-off transition, figures 5, 9 v l > 2.3v 18 ns receiver (c l = 15pf) t plh_rcv low-to-high transition, figures 6,10 v l > 2.3v 20 differential receiver propagation delay t phl_rcv high-to-low transition, figures 6,10 v l > 2.3v 20 ns t plh_se low-to-high transition, figures 6,10 18 single-ended receiver propagation delay t phl_se high-to-low transition, figures 6,10 18 ns t phz_se high-to-off transition, figure 7 v l > 2.3v 20 single-ended receiver disable delay t plz_se low-to-off transition, figure 7 v l > 2.3v 20 ns t pzh_se off-to-high transition, figure 7 v l > 2.3v 22 single-ended receiver enable delay t pzl_se off-to-low transition, figure 7 v l > 2.3v 22 ns note 1: parameters are 100% production tested at +25 c, unless otherwise noted. limits over temperature are guaranteed by design.
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors _______________________________________________________________________________________ 5 typical operating characteristics (v bus = +5v, v l = +3.3v, t a = +25 c, unless otherwise noted.) 4 8 6 12 10 14 16 18 20 1.2 1.8 2.1 1.5 2.4 2.7 3.0 3.3 3.6 differential receiver propagation delay vs. v l MAX13342E toc01 v l (v) propagation delay (ns) t a = +85 c t a = +25 c t a = -40 c 0 8 4 2 6 12 10 14 16 18 20 4.0 4.3 4.6 4.9 5.2 5.5 differential receiver propagation delay vs. v bus MAX13342E toc02 v bus (v) propagation delay (ns) t a = +85 c t a = +25 c t a = -40 c 10 18 14 12 16 22 20 24 26 28 30 1.2 1.8 2.4 3.0 1.5 2.1 2.7 3.3 3.6 single-ended receiver propagation delay vs. v l MAX13342E toc03 v l (v) propagation delay (ns) oe = sus = high t a = +85 c t a = +25 c t a = -40 c 0 8 4 2 6 12 10 14 16 18 20 4.0 4.3 4.6 4.9 5.2 5.5 single-ended receiver propagation delay vs. v bus MAX13342E toc04 v bus (v) propagation delay (ns) oe = sus = high t a = +85 c t a = +25 c t a = -40 c 0 0.4 0.2 0.1 0.3 0.6 0.5 0.7 0.8 0.9 1.0 -40 -15 10 35 60 85 transmitter skew vs. temperature MAX13342E toc05 temperature ( c) transmitter skew (ns) 0.6 1.0 0.8 0.7 0.9 1.2 1.1 1.3 1.4 1.5 -40 -15 10 35 60 85 receiver skew vs. temperature MAX13342E toc06 temperature ( c) transmitter skew (ns) 8 16 12 10 14 20 18 22 24 26 0 22 66 110 154 44 88 132 176 198 220 v l supply current vs. d+/d- capacitance MAX13342E toc07 capacitance (pf) v l supply current (ma) 1.0 1.2 1.1 1.4 1.3 1.5 1.6 1.7 0 22 66 110 154 44 88 132 176 198 220 v bus supply current vs. d+/d- capacitance MAX13342E toc08 capacitance (pf) v bus supply current (ma) v l = 2.5v 20 28 24 22 26 32 30 34 38 36 40 4.0 4.3 4.6 4.9 5.2 5.5 v bus suspend current vs. v bus supply voltage MAX13342E toc09 v bus (v) v bus supply current ( a) t a = +85 c t a = +25 c t a = -40 c
typical operating characteristics (continued) (v bus = +5v, v l = +3.3v, t a = +25 c, unless otherwise noted.) MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 6 _______________________________________________________________________________________ MAX13342E/max13345e transmitting MAX13342E toc10 d+ d- 2v/div dat 2v/div (2v/div) seo 20ns/div MAX13342E/max13345e receiving MAX13342E toc11 d- d+ 2v/div 2v/div 2v/div dat 2v/div seo 100ns/div MAX13342E/max13345e bus detection MAX13342E toc12 1v/div vbus 2v/div bd 4 s -1 0 1 2 3 4 020 10 30 40 50 60 70 80 eye diagram time (ns) d+ and d- (v) MAX13342E toc13
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors _______________________________________________________________________________________ 7 pin description pin tdfn ucsp name function 1b1v trm regulated output voltage. v trm provides a 3.3v output derived from v bus . bypass v trm to gnd with a 1f (min) low-esr capacitor, such as ceramic or plastic film types. v trm provides power to internal circuitry and the internal d+ pullup resistor. do not use v trm to power external circuitry. these usb transceivers can also be powered by an externally regulated 3.3v supply connected to both v bus and v trm. 2a1v l system-side power-supply input. connect v l to the systems logic-level power supply. bypass v l to gnd with a 0.1f (min) low-esr ceramic capacitor. 3 a2 se0 logic-side data input/output. se0 operates as an input when oe is low and as an output when oe is high. as an input, when se0 is active high, d+ and d- are both driven low. as an output, se0 goes active high when both d+ and d- are low. (see tables 3 and 4.) 4 a3 dat logic-side data input/output. dat operates as an input for data on d+/d- when oe is low. dat operates as the output of the differential receiver on d+/d- when oe is high. (see tables 3 and 4.) 5, 12 n.c. no connection. leave n.c. unconnected. n.c. is not internally connected. 6 b3 sus suspend input. drive sus low for normal transceiver operation. drive sus high for low-power state. 7 a4 bd usb detector output. a high on bd indicates that v bus is present. 8b4 oe output enable. oe controls the usb transmitter outputs (d+/d-) and the interface signals (dat, se0) when in usb mode. drive oe high to operate d+/d- as inputs and to operate the logic interface signals as outputs. drive oe low to operate d+/d- as outputs and to operate the logic interface signals as inputs. 9 c4 gnd ground 10 c3 d- negative usb differential data input/output. d- is wired to the usb connector directly (max13345e) or through a series resistor (MAX13342E). d- operates as an input when oe is high and as an output when oe is low. 11 c2 d+ positive usb differential data input/output. d+ is wired to the usb connector directly (max13345e) or through a series resistor (MAX13342E). d+ operates as an input when oe is high and as an output when oe is low. 13 b2 enum enumerate. drive enum high to connect the internal 1.5k ? resistor from d+ to v trm . drive enum low to disconnect the internal 1.5k ? resistor. 14 c1 v bus usb-side power-supply input. connect v bus to the incoming usb power supply. bypass v bus to gnd with a 1f ceramic capacitor. ep ep exposed paddle. connect ep to gnd.
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 8 _______________________________________________________________________________________ detailed description the MAX13342E/max13345e usb-compliant trans- ceivers are designed to minimize the area and external components required to interface low-voltage asics to usb. the devices comply with the usb 2.0 specifica- tion for full-speed (12mbps) operation. the transceivers include an internal 3.3v regulator, an internal 1.5k ? d+ pullup resistor, and built-in 15kv (hbm) esd protec- tion circuitry to protect d+, d-. figure 1 is the MAX13342E/max13345e functional diagram. the MAX13342E has controlled output impedance of 12 ? (max) on d+/d-, allowing the use of external switches to multiplex two different usb devices onto a single usb connector. the max13345e uses internal series resistors on d+/d- to allow direct interface to the usb connector. a low- power mode reduces current consumption to less than 45a. an enumerate function controls connection of the internal d+ pullup resistor. the MAX13342E/max13345e are equipped with dat and se0 interface signals and support the 3-wire usb tranceiver interface. although the 3-wire interface is commonly associated with usb on-the-go trans- ceivers, the MAX13342E/max13345e support usb peripherals only. these transceivers provide a usb v bus detection function that monitors the presence of usb v bus and signals the event. level translator and logic d+ d- bd oe v l ldo regulator v trm v bus MAX13342E max13345e enum sus dat seo max13345e figure 1. MAX13342E/max13345e functional diagram
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors _______________________________________________________________________________________ 9 interface the MAX13342E/max13345e control signals are used to control the usb d+/d- lines. v l powers the logic- side interface and sets the input and output thresholds of these signals. the control signals for the MAX13342E and max13345e are dat, se0, and oe . power-supply configuration normal operating mode see table 1 for various power-supply configurations. v bus supplies power to the usb transceivers. connect v bus to a +4v to +5.5v supply. connect v l to a +2.3v to +3.6v supply. v bus is typically connected directly to the usb connector. an internal regulator provides 3.3v to internal circuitry, and a regulated 3.3v output at v trm , in addition to powering the internal d+ pullup resistor. the MAX13342E and max13345e can be powered by connecting both v bus and v trm to a 3.3v external regulator. low-power mode operate the transceivers in low-power mode by assert- ing sus high. in low-power mode, the usb differential receiver is turned off and v bus consumes less than 45a of supply current. the single-ended d+ and d- receivers are still active when driving sus high. sharing mode connect v l to a system power supply and leave v bus (or v bus and v trm ) unconnected or connected to gnd. d+ and d- are tri-stated, allowing other circuitry to share the usb d+ and d- line. v l consumes less than 5a of supply current. when operating the trans- ceivers in sharing mode, the sus input is ignored, and the interface signals (se0, dat) are high impedance. disable mode connect v bus to a system power supply and leave v l unconnected or connect to ground. in disable mode, d+ and d- are tri-stated, and v bus and/or v trm (or v bus and v trm ) consume less than 25a. when oper- ating the transceivers in disable mode, oe , sus, and inputs to the interface control signals are ignored. (see table 2.) v bus (v) v trm (v) v l (v) configuration notes +4.0 to +5.5 +3.0 to +3.6 output +2.3 to +3.6 normal mode +4.0 to +5.5 +3.0 to +3.6 output gnd or floating disable mode table 2 gnd or floating high z +2.3 to +3.6 sharing mode table 2 inputs/outputs disable mode sharing mode v bus / v trm 4v to 5.5v floating or connected to gnd v l floating or connected to gnd 2.3v to 3.6v input d+ and d- high impedance high impedance dat, se0 high impedance high impedance sus high impedance high impedance bd low low table 1. power-supply configuration table 2. disable-mode and sharing-mode connection
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 10 ______________________________________________________________________________________ 3-wire dat/se0 interface the MAX13342E/max13345e use dat and se0 to drive data or a single-ended zero onto the d+/d- lines. when oe is low, se0 is an input and functions as a single-ended zero driver. when se0 is high, both d+ and d- are driven low. when se0 is driven low, the d+/d- outputs are controlled by dat. dat is used to send data on d+/d- when both oe and se0 are low. when dat is high, d+ is driven high and d- is driven low. when dat is low, d+ is driven low and d- is driven high. in receive mode ( oe = high), dat is the output of the differential receiver connected to d+ and d-. se0 only goes active high when both d+ and d- are low. control signals usb detection the ma13342e/max13345e usb detection function indicates that v bus is present. the MAX13342E/ max13345e push-pull bus detection output (bd) moni- tors v bus , and asserts high when v bus and v l are pre- sent. bd asserts low if v bus is less than +3.6v and enters sharing mode. oe oe controls the direction of communication when v l and v bus are both present. when oe is low, dat and se0 operate as logic inputs and d+/d - are outputs. when oe is high, dat and se0 operate as logic out- puts and d+/d- are inputs. sus sus determines whether the MAX13342E/max13345e operate in normal mode or in suspend mode. drive sus low for normal operation. drive sus high to enable suspend mode. in suspend mode, the single-ended receivers (d+/d-) are active to detect a wake-up event. supply current decreases to less than 45a in suspend mode. the MAX13342E/max13345e can transmit data on d+ and d- while in suspend mode. this function is used to signal a remote wake-up event. enum a 1.5k ? pullup resistor on d+ is used to indicate full- speed (12mbps) operation. drive enum high to con- nect the internal pullup resistor from d+ to v trm . drive enum low to disconnect the internal pullup resistor from d+ to v trm . d+ and d- d+ and d- are bidirectional signals and are esd pro- tected to 15kv (hbm). oe controls the direction of d+ and d- when in usb normal mode (tables 3 and 4). v trm an internal linear regulator generates the v trm voltage (+3.3v typ). v trm derives power from v bus (see the power-supply configuration section). v trm powers the internal usb circuitry and provides the pullup voltage for the internal 1.5k ? resistor. bypass v trm to gnd with a 1f ceramic capacitor as close to the device as possible. do not use v trm to provide power to external circuitry.
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors ______________________________________________________________________________________ 11 applications information usb data transfer transmitting data the MAX13342E/max13345e transmit usb data to the usb differentially on d+ and d- when oe is low. the d+ and d- outputs are determined by se0 and dat (see table 3). receiving data drive oe high and sus low to receive data on d+/d-. differential data received on d+ and d- appear at dat. se0 goes high only when both d+ and d- are low (table 4). external resistors (MAX13342E) the MAX13342E provides low internal resistance on d+/d-. two external series resistors for impedance matching are required for usb. place the resistors in between the MAX13342E and the usb connector (see figure 2). external capacitors use three external capacitors for proper operation. bypass v l to gnd with a 0.1f ceramic capacitor. bypass v bus to gnd with a 1f ceramic capacitor. bypass v trm to gnd with a 1f (min) ceramic or plas- tic capacitor. place all capacitors as close to the device as possible. ucsp application information for the latest application details on ucsp construction, dimensions, tape carrier information, printed circuit board (pcb) techniques, bump-pad layout, and recom- mended reflow temperature profile, as well as the latest information on reliability testing results, refer to application note 1891: ucsp a wafer-level chip- scale package available on maxim s website at www.maxim-ic.com/ucsp. ( oe = 0, sus = 0) inputs outputs dat se0 d+ d- 0001 0100 1010 1100 table 3. transmit truth table ( oe = 1, sus = 0) inputs outputs d+ d- dat se0 0 0 *dat 1 0 1 **0 0 1 0 **1 0 11x0 table 4. receive truth table * last state ** d+/d- differential receiver output x = undefined
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 12 ______________________________________________________________________________________ esd protection the MAX13342E/max13345e feature 15kv (hbm) esd protection on d+ and d-. the esd structures withstand high esd in all states: normal operation, suspend, and powered down. for the 15kv esd structures to work correctly, a 1f or greater capacitor must be connected from v trm to gnd. v bus and d+/d- are characterized for protection to the following limits: 15kv using the human body model 8kv using the iec 61000-4-2 contact discharge method 8kv using the iec 61000-4-2 air-gap method esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 11 shows the human body model, and figure 12 shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the test device through a 1.5k ? resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment; it does not specifi- cally refer to integrated circuits. the MAX13342E/ max13345e help the user design equipment that meets level 4 of iec 61000-4-2, without the need for additional esd-protection components. the major difference between tests done using the human body model and iec 61000-4-2 is a higher peak current in iec 61000-4- 2 because series resistance is lower in the iec 61000- 4-2 model. hence, the esd withstand voltage measured to iec 61000-4-2 is generally lower than that measured using the human body model. figure 13 shows the iec 61000-4-2 model. the air-gap discharge method involves approaching the device with a charged probe. the contact discharge method connects the probe to the device before the probe is energized. MAX13342E system voltage supply v bus v l system interface dat seo gnd d- d+ gnd d- d+ v trm sus enum oe usb connector 31.6 ? 31.6 ? usb power 0.1 f 1.0 f 1.0 f bd figure 2. adding external resistors to the usb connector for the MAX13342E
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors ______________________________________________________________________________________ 13 v ohd v old 90% 10% 90% 10% t fr , t lr t ff , t lf figure 3. rise and fall times dat connected to gnd, se0 connected to gnd. d+ pulled to 3.0v with 150 ? . dat connected to v l , se0 connected to gnd. d+ pulled to gnd with 150 ? . dat connected to v l , se0 connected to gnd. d- pulled to v l with 150 ? . dat connected to gnd, se0 connected to gnd. d- pulled to gnd with 150 ? . t pzh_drv t pzl_drv t pzh_drv t pzl_drv t phz_drv t plz_drv t phz_drv t plz_drv d+ d+ d- d- oe figure 5. enable and disable timing, transmitter dat seo d- d+ t plh_drv t phl_drv v crs_f , v crs_l rise/fall times < 4ns figure 4. timing of dat, se0 to d+ and d- timing diagrams/test circuits +3v 0v dat/seo v l d+/d- t plh_rcv , t plh_se t phl_rcv , t phl_se input rise/fall time < 4ns figure 6. d+/d- to dat, se0 propagation delays
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 14 ______________________________________________________________________________________ d+ connected to gnd, d- connected to +3.0v. dat pulled to v l with 330 ? . d+ connected to +3.0v, d- connected to gnd. dat pulled to gnd with 330 ? . d+ connected to +3.0v, d- connected to gnd. se0 pulled to v l with 330 ? . d+ connected to gnd, d- connected to gnd. se0 pulled to gnd with 330 ? . t pzh_se t pzl_se t pzh_se t pzl_se t phz_se t plz_se t phz_se t plz_se dat dat se0 se0 oe figure 7. receiver enable and disable timing d+/d- dut 31.6 ? 15k ? 50pf test point for the MAX13342E load for: 1) enable time (d+/d-) measurement 2) dat/seo to d+/d- propagation delay 3) d+/d- rise/fall times figure 8. load for transmitter propagation delay, enable time, transmitter rise/fall times d+/d- dut 31.6 ? 220 ? 50pf test point for the MAX13342E notes: 1) v = 0 for t phz 2) v = v trm for t plz figure 9. load for disable time measurements dat/seo dut 15pf test point load for: 1) d+/d- to dat/seo propagation delays 2) dat/seo rise/fall times figure 10. load for receiver propagation delay and receiver rise/fall times
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors ______________________________________________________________________________________ 15 charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m ? r d 1.5k ? high- voltage dc source device under test figure 11. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 12. human body model current waveform charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50m ? to 100m ? r d 330 ? high- voltage dc source device under test figure 13. iec 61000-4-2 esd test model
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors 16 ______________________________________________________________________________________ MAX13342E max4717 system voltage supply v bus v l system interface bd dat seo gnd d- d+ v trm com1 nc1 no1 nc2 no2 in1, in2 sus enum oe gpio com2 multimedia processor usb connector 0.1 f 1 f 1 f 31.6 ? 31.6 ? typical application circuit pin configurations top view (bump side down) 2.0mm x 1.5mm ucsp dat seo bd v l 1 a b c 234 v bus gnd d+ v trm sus oe enum d- max13345e MAX13342E MAX13342E max13345e 3mm x 3mm tdfn top view 245 13 11 10 enum d+ d- v l dat n.c. 1 14 v bus v trm 3 12 n.c. se0 6 9 gnd sus 7 8 oe bd *connect ep to gnd *ep + + chip information process: bicmos
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors ______________________________________________________________________________________ 17 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 6, 8, &10l, dfn thin.eps h 1 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code n d2 e2 e jedec spec b [(n/2)-1] x e package variations 0.25 min. k a2 0.20 ref. 2.30?0.10 1.50?0.10 6 t633-1 0.95 bsc m o229 / weea 1.90 ref 0.40?0.05 1.95 ref 0.30?0.05 0.65 bsc 2.30?0.10 8 t833-1 2.00 ref 0.25?0.05 0.50 bsc 2.30?0.10 10 t1033-1 2.40 ref 0.20?0.05 - - - - 0.40 bsc 1.70?0.10 2.30?0.10 14 t1433-1 1.50?0.10 1.50?0.10 mo229 / weec mo229 / weed-3 0.40 bsc - - - - 0.20?0.05 2.40 ref t1433-2 14 2.30?0.10 1.70?0.10 t633-2 6 1.50?0.10 2.30?0.10 0.95 bsc m o229 / weea 0.40?0.05 1.90 ref t833-2 8 1.50?0.10 2.30?0.10 0.65 bsc m o229 / weec 0.30?0.05 1.95 ref t833-3 8 1.50?0.10 2.30?0.10 0.65 bsc m o229 / weec 0.30?0.05 1.95 ref -drawing not to scale- h 2 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm 2.30?0.10 mo229 / weed-3 2.00 ref 0.25?0.05 0.50 bsc 1.50?0.10 10 t1033-2
MAX13342E/max13345e 3-wire interface full-speed usb transceivers with/without internal series resistors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 12l, ucsp 4x3.eps f 1 1 21-0104 package outline, 4x3 ucsp

▲Up To Search▲

Price & Availability of MAX13342E

	To Download MAX13342E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .